Users & Projects

This page lists a number of MyHDL users and projects. The best thing you can do to support MyHDL is to add your project here and let people know about it!

Dillon Engineering uses MyHDL in its verification flow. Read more about it here.

• Using MyHDL and eispice:How to connect eispice and MyHDL.
• Cordic Calculations: enhanced version of the cookbook example (Cordic-based Sine Computer).
• Sine Wave Generator using Sigma Delta DAC: using Cordic Calculations and DSX1000: Delta-Sigma DAC core
• Cosimulation using Quartus Simulator
• Get rid of the Signal: Proposal for syntax enhancement of MyHDL
• Interactive Simulation with IPython

Christopher L. Felton uses MyHDL for student projects at the University of Colorado, Colorado Springs. Using MyHDL for DSP algorithm to hardware implementations. Also uses MyHDL in a USB FPGA project (small example).

David Brochart uses MyHDL in his open-source Turbo Decoder project.

David MacQuigg uses MyHDL in a Lab Course at the university of Arizona.

Jean Demartini uses MyHDL to support a teaching course “Programmable Digital Processor Architecture” at the Engineering School of the University of Nice Sophia-Antipolis (ESINSA). The different supports of this course are available (in french) for downloading at a not so nice perso web site. Differents MyHDL models will be soon available too including:

• an elementary Von Neumann semantical engine,
• a simple microcoded Von Neumann engine,
• a Havard microcoded engine,
• Pipelined and superscalar processor,
• etc.

Chun Lin Zhang uses MyHDL as the HVL in his ASIC project.

Nick Patavalis has written a simulator for the MU0 processor in MyHDL. (Note: the source code can be found from Nick's announcement in the MyHDL newsgroup.)

George Pantazopoulos has built an digital/analog hybrid synthesizer (codenamed the PhoenixSID 65x81) based on the Commodore 64's 6581 'SID' sound chip.

George has also released some open-source MyHDL IP cores, and has worked on an extension library to MyHDL.

George's personal page