Welcome to MyHDL

MyHDL - From Python to Silicon!

Welcome to the MyHDL website. MyHDL is an open source Python package that lets you go from Python to silicon. With MyHDL, you can use Python as a hardware description and verification language. Furthermore, you can convert implementation-oriented MyHDL code to Verilog automatically, and take it to a silicon implementation from there.

On this website, you will find everything you need to get started - and to keep going - with MyHDL. Have fun!

Latest News: MyHDL now has a Logo.
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